1. Field of the Invention
The present invention relates to a digital filter architecture, and, more particularly, to a digital filter with single-bit multipliers in a MASH delta-sigma modulator.
2. Description of the Related Art
Many current applications employ digital sampling of analog signals with over-sampling. For example, analog-to-digital (AID) converters may typically employ an over-sampling architecture. Over-sampling is usually performed at a rate faster than conventional A/D converters by a factor of 2.sup.R, R an integer greater than 1. A/D converters, or other applications, employing over-sampling generate a large number of samples adding semi-redundant information for subsequent processing. Semi-redundant information may allow for better recovery of a base signal from a quantized signal. Consequently, digital decimation may be utilized to decrease the rate of samples. For digital decimation, two processing steps occur on the oversampled input sequence x[n] at sample rate .function..sub.s. First, the input sequence is filtered to remove out-of-band noise. Second, the filtered sequence is downsampled in a decimator from the high sample rate .function..sub.s to a downsampled rate off .function.s/M, where M is the decimation factor that usually equivalent to 2.sup.R.
Analog signals are first processed by an analog modulator, which may be a delta-sigma modulator. While the delta-sigma modulator operates over the baseband, the delta-sigma modulator adds significant quantization noise outside of the baseband. The filtering step is utilized to filter out this quantization noise, and noise shaping is employed prior to filtering to improve performance. Noise shaping operates on the quantization noise of the oversampled sequence, which may be white, Gaussian noise, and reduces quantization noise power in the frequency band of the desired signal by moving the noise power to bands outside. Therefore, filtering by the delta-sigma modulator usually consists of, for example, a high-pass filtering of the added quantization noise signal (noise shaping), followed by, for example, low-pass filtering of the quantization noise signal (noise filtering). Other types of filtering operations on the quantization noise may occur, such as in, for example, band-pass delta-sigma modulators.
One type of delta-sigma modulator employs a MASH architecture. The MASH architecture uses at least two stages, each stage including a low-order, noise-shaping filter and a bit-quantizer (i.e., a comparator). The output sequences of the stages are combined so that the low-order filters operate in cascade to provide a high-order noise-shaping filter (i.e., an N-order noise-shaping filter, N an integer greater than 1). The order of the noise-shaping filter in the MASH delta-sigma modulator may typically be the sum of the orders of the lower-order, noise-shaping stages. Such MASH delta-sigma modulator may commonly be a two-stage delta-sigma modulator having a first stage including a first- or second-order noise-shaping filter and a second stage including a first- or second-order noise-shaping filter. For each order (i.e., high-pass) filter, noise shaping typically transforms the white (flat) noise spectrum of the added quantization noise to a spectrum having a ramp (i.e., positive) noise spectrum, typically on the order of 20 dB per decade. Consequently, third order noise shaping provides, for example, a 60 dB per decade noise-shaped quantization noise spectrum. The digital filter following the noise shaping stages may operate as a low pass infinite impulse response (IIR) filter. The IIR filter desirably has a filter order at least one order higher than the nose-shaping filter (i.e., -80 dB per decade). The digital filter is typically implemented as a Finite Impulse Response (FIR) filter approximating the frequency response of the IIR filter since the FIR filter provides a linear or flat delay response (constant group delay).
A MASH delta-sigma modulator 100 of the prior art is shown in FIG. 1 and includes cascaded filter sections 101, preprocessing stage 106, digital filter 120, which is a conventional FIR filter, and decimator 130. The MASH delta-sigma modulator 100 also typically includes cascaded filter sections 101, each section providing first and/or second order noise-shaping and one-bit quantization of the received input sequence x[n]. As shown in FIG. 1, MASH delta-sigma modulator 100 is a two-stage MASH delta-sigma modulator comprising first noise-shaping stage 102 and second noise-shaping stage 104. Since MASH delta-sigma modulator 100 includes cascaded filter sections, pre-processing stage 106 combines the output signals y.sub.1 [n] and y.sub.2 [n] of the first and second noise-shaping stages 102 and 104 so as to remove lower order, noise-shaped components of the quantization noise signal, leaving an output sequence y.sub.F [n] representing the signal with only higher-order noise-shaped components. Digital filter 120 may be a FIR filter having K-taps (K an integer) each of the K-taps representing the filter coefficients. Decimator 130 downsamples the filtered sequence of the digital filter 120 by a decimate-by-M operation on the sequence provided by digital filter 120.
An implementation of the two-stage, MASH delta-sigma modulator 100 is shown in FIG. 2. First noise-shaping stage 102 includes two integration feedback loops 220 and 222, respectively, followed by bit-quantizer 224. Second noise-shaping stage 104 includes a single integration feedback loop 230, followed by bit-quantizer 232. Each bit-quantizer 224 and 232 is a one-bit quantizer operating on the filtered input signal x[n].
First noise-shaping stage 102 receives an input sequence x[n] and provides first output sequence y.sub.1 [n]. The single integration feedback loop 230 of the second noise-shaping stage 104 receives the second order (filtered) output of integration feedback loop 222 of the first noise-shaping stage and provides a second output sequence y.sub.2 [n]. Values of the first and second output sequences y.sub.1 [n] and y.sub.2 [n] are each single bit, binary values (logic "1" or "0") provided by the bit-quantizers 224 and 232, respectively.
As would be apparent to one skilled in the art, first noise-shaping stage 102, as shown in FIG. 2, includes a second-order, noise-shaping (second-order, high-pass) filter and the second noise-shaping stage 104 includes a first-order noise-shaping (first-order, high-pass) filter. A two-stage MASH delta-sigma modulator may be implemented with a variety of noise-shaping filter stages. For example, two first-order noise-shaping filters or two second-order noise-shaping filters may be employed. However, noise-shaping filters providing the baseband signal with an out-of-band noise component noise-shaped above the fourth order are typically not preferred since circuits having higher-order filter loops in cascade are either unstable or conditionally stable. For many applications, an FIR filter for digital filter 120 operates on the baseband signal having a third-order, noise-shaped quantization noise signal.
As shown in FIG. 2, the first noise-shaping stage 102 provides a second order noise component in the output value y.sub.1 [n]. Since the second noise-shaping stage 104 receives the second-order filtered sequence from integration feedback loop 222, the output sequence y.sub.2 [n] of the bit-quantizer 232 includes both a first order (noise-shaped) quantization noise component and a third order (noise-shaped) quantization noise component. Consequently, pre-processing stage 106 removes these first- and second-order quantization noise components from the combined first and second output sequences y.sub.1 [n] and y.sub.2 [n], leaving only the third order quantization noise component in the sequence y.sub.F [n], provided to digital filter 120.
The combining operation of the pre-processing stage 106 is shown in FIG. 2 for the two-stage, third-order MASH delta-sigma modulator. As would be apparent to one skilled in the art, the first output sequence y.sub.1 [n] is subject to a first order differentiation in operator 259, and the second output sequence y.sub.2 [n] is first multiplied by four (for normalizing purposes) in gain multiplier 260 and the first noise component subtracted in combiner 261 using the differentiated first output sequence y.sub.1 [n]. The remainder of the second output sequence y.sub.2 [n] is then processed with both a first and second order differentiation operator 262 leaving a sequence having only first and third order quantization noise components. The differentiated first output sequence y.sub.1 [n] is then also used to subtract the remaining first-order quantization noise component in combiner 263 that provides y.sub.F [n] with only a third-order quantization noise component.
The pre-processing stage 106 of the prior art receives and combines the two, one-bit binary values provided by the first and second noise-shaping sections 102 and 104. Since each value of the output sequence y.sub.F [n] of pre-processing stage 106 has at least four possible values, at least two bits must be employed to represent each value of y.sub.F [n]. The FIR digital filter 120 must then apply each of the coefficients to the multi-bit values of y.sub.F [n]. This application by FIR digital filter 120 results in a multi-bit multiplication of the value of y.sub.F [n] with the taps (coefficients) of FIR filter 108. Since the input to the FIR filter 108 has several values, the exemplary FIR digital filter 120 must include a chain of multi-bit delays 250 and multipliers 251capable of multiplying multi-bit values. An exemplary K-tap FIR filter having tap coefficients T.sub.1 through T.sub.K for digital filter 120 of the prior art is shown in FIG. 2.
A MASH architecture for a delta-sigma modulator has a benefit of unconditional stability. Consequently, monitoring of the circuit for stability may be eliminated, and the circuit may be easily reset if an unusual event should occur. A disadvantage to this architecture, however, is that sequences of multi-bit values are presented to the digital filter removing quantization noise. Multi-bit multipliers are typically costly in terms of integrated circuit area and implementation complexity.